The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a FinFET device containing a composite spacer structure that includes an inner low-k dielectric material portion and an outer nitride material portion.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs), is the next step in the evolution of CMOS devices. FinFETs are non-planar semiconductor devices which include at least one semiconductor fin protruding from a surface of a substrate. A gate dielectric can be formed in direct physical contact with each vertical sidewall of the at least one semiconductor fin and, optionally, in direct physical contact with a topmost surface of the semiconductor fin. A gate conductor can be formed on the gate dielectric and straddling a portion of the at least one semiconductor fin. FinFETs can increase the on-current per unit area relative to planar field effect transistors.